1. Field of the Invention
The present invention relates to a signal reading circuit for reading out a voltage signal to a signal line through a read transistor and for outputting the signal.
2. Related Background Art
FIG. 1A is a circuit diagram showing an example of a conventional signal reading circuit. FIG. 1B is a timing chart for explaining the operation of such a reading circuit.
In FIG. 1A, by setting a pulse .phi..sub.t to the high level for a predetermined period of time, a transfer transistor Q.sub.t is turned on, so that signals S.sub.1, S.sub.2, S.sub.3, . . . of sensors (not shown) are transferred to and accumulated in each capacitor C.sub.t. In this state, scan pulses .phi..sub.11, .phi..sub.12, . . . are successively output from a shift register 102 to sequentially turn on read transistors Q.sub.s, thereby reading out the signals S.sub.1, S.sub.2, S.sub.3, . . . , stored in the capacitors C.sub.t, to a signal line 101. However, since the signal line 101 has a capacitance C.sub.h, the signals which are obtained by dividing the storage signals S.sub.1, S.sub.2, S.sub.3, . . . by the capacitance of the capacitor C.sub.t and the capacitance C.sub.h are read out to the signal line 101.
As shown in FIG. 1A, pulses .phi..sub.s, .phi..sub.1, and .phi..sub.2 are input to the shift registor 102. The shift register 102 then outputs a scan pulse, synchronously with the pulse .phi..sub.1, by the start pulse .phi..sub.s.
The signal read to the signal line 101 is output through an amplifier A. Whenever each signal is output, a reset transistor Q.sub.r is turned on, thereby resetting the signal line 101 to ground potential. The pulse .phi..sub.2 which is also input to the shift register 102 is input to a gate electrode of the reset transistor Q.sub.r. The circuit elements and sensors shown in FIG. 1A are formed on the same semiconductor substrate.
However, in the conventional example, the noise components caused by the scan pulses .phi..sub.11, .phi..sub.12, . . . are added to the signal which is output from the amplifier A. Therefore, when this signal reading circuit is used in e.g., an image pickup apparatus, there is a problem such that those noise components appear as fixed pattern noise. This point will now be explained with reference to a waveform diagram of a signal line voltage V.sub.0 shown in FIG. 1B. The signal components are omitted in the waveform V.sub.0 for convenience of explanation.
First, for a period of time T.sub.c when the pulse .phi..sub.2 is at the high level, the reset transistor Q.sub.r is turned on and the voltage V.sub.0 of the signal line 101 is set to ground potential GND. When the pulse .phi..sub.2 falls to the low level and the transistor Q.sub.r is turned off, since an overlap capacitance C.sub.s2 exists, the trailing amount of the pulse .phi..sub.2 is capacitively divided by C.sub.s2 and C.sub.h, so that the voltage V.sub.0 of the signal line 101 decreases lower than GND by only the level corresponding to the trailing amount (oscillating component b).
However, the amplitude of the oscillating component b is always constant because it depends on the capacitance C.sub.s2.
Next, when the scan pulse .phi..sub.11 is input to the transistor Q.sub.s synchronously with the pulse .phi..sub.1 (for a period of time T.sub.t), since the overlap capacitance C.sub.s of the transistor Q.sub.s exists, the leading amount of the scan pulse .phi..sub.11 is capacitively divided by C.sub.s and C.sub.h, so that the voltage V.sub.0 of the signal line 101 increases by only the level of the leading amount (the voltage V.sub.r). The trailing amount is also capacitively divided, so that the voltage V.sub.0 of the signal line 101 drops by only the level corresponding to the leading amount (voltage V.sub.t) (oscillating component a).
In this manner, the sensor signal S.sub.1 is read out to the signal line 101 through the read transistor Q.sub.s and output from the amplifier A. Thus, the reset transistor Q.sub.r is again turned on by the pulse .phi..sub.2. In a manner similar to the above, the sensor signals S.sub.2, S.sub.3, . . . are sequentially output.
However, the scan pulses .phi..sub.11, .phi..sub.12, . . . which are output synchronously with the pulses .phi..sub.1 are input to the gate of individual read transistor Q.sub.s, so that the following problems occur.
That is, the overlap capacitances of the read transistors have a certain variation due to a variation in semiconductor processes.
Therefore, the oscillating components a are not uniform. Assuming that a variation of the capacitances C.sub.s is .DELTA.C.sub.s, a variation in oscillating components a is EQU .DELTA.v.sub.n =.DELTA.C.sub.s .multidot.V.sub..phi. /(C.sub.s +C.sub.h)
When it is now assumed that
C.sub.h =5 pF PA1 C.sub.s =0.02 pF PA1 .DELTA.C.sub.s =C.sub.s .times.0.01 PA1 V.sub.100 =5 V,
the variation .DELTA.v.sub.n in oscillating components a becomes .DELTA.v.sub.n =0.2 mV. This variation appears as a fixed pattern noise in the vertical direction on the image and causes the picture quality to deteriorate.